I2C Protocol

I²C (Inter-Integrated Circuit) is a master slave, single-ended, serial bus used for attaching low-speed peripherals to computer motherboards and embedded systems. I²C uses only two bidirectional open-drain lines, Serial Data Line (SDA) and Serial Clock Line (SCL), pulled up with resistors. Typical voltages used are +5 V or +3.3 V. The I²C reference design has a 7-bit or a 10-bit address space. Common I²C bus speeds are the 100 kbit/s standard mode, 10 kbit/s low-speed mode, 400 kbit/s Fast mode, 1 Mbit/s Fast mode and 3.4 Mbit/s High Speed mode. The maximum number of nodes is limited by the address space, and also by the total bus capacitance of 400 pF, which restricts practical communication distances.

i2cA sample schematic with one master (a microcontroller), three slave nodes (an ADC, a DAC, and a microcontroller), and pull-up resistors Rp.

The I2C bus has two roles for nodes:

Master and Slave:

  • Master node — node that generates the clock and initiates communication with slaves
  • Slave node — node that receives the clock and responds when addressed by the master

There may be four potential modes of operation for a given bus device, although most devices only use a single role and its two modes:

  • master transmit — master node is sending data to a slave
  • master receive — master node is receiving data from a slave
  • slave transmit — slave node is sending data to the master
  • slave receive — slave node is receiving data from the master

The master is initially in master transmit mode by sending a start bit followed by the 7-bit address of the slave it wishes to communicate with, which is finally followed by a single bit representing whether it wishes to write(0) to or read(1) from the slave.

If the slave exists on the bus then it will respond with an ACK bit (active low for acknowledged) for that address. The master then continues in either transmit or receive mode (according to the read/write bit it sent), and the slave continues in its complementary mode (receive or transmit, respectively).

The address and the data bytes are sent most significant bit first. The start bit is indicated by a high-to-low transition of SDA with SCL high; the stop bit is indicated by a low-to-high transition of SDA with SCL high. All other transitions of SDA take place with SCL low.

If the master wishes to write to the slave then it repeatedly sends a byte with the slave sending an ACK bit. (In this situation, the master is in master transmit mode and the slave is in slave receive mode.)

If the master wishes to read from the slave then it repeatedly receives a byte from the slave, the master sending an ACK bit after every byte but the last one. (In this situation, the master is in master receive mode and the slave is in slave transmit mode.)
The master then either ends transmission with a stop bit, or it may send another START bit if it wishes to retain control of the bus for another transfer (a “combined message”).

Key symbols
S (1 bit) : Start bit
P (1 bit) : Stop bit
R/W (1 bit) : Read/Write bit. Rd equals 1, Wr equals 0.
A, NA (1 bit) : Accept and reverse accept bit.
Addr (7 bits): I2C 7 bit address. Can be expanded as usual to get a 10 bit I2C address.
Comm (8 bits): Command byte, a data byte which often selects a register on the device.
Data (8 bits): A plain data byte.
Count (8 bits): A data byte containing the length of a block operation.
[..]: Data sent by I2C device, as opposed to data sent by the host adapter.

Simple send transaction
This corresponds to i2c_master_send.
S Addr W [A] Data [A] Data [A] … [A] Data [A] P

Simple receive transaction
This corresponds to i2c_master_recv.
S Addr R [A] [Data] A [Data] A … A [Data] NA P

i2c data transfer

  1. Data Transfer is initiated with a START bit (S) signaled by SDA being pulled low while SCL stays high.
  2. SDA sets the 1st data bit level while keeping SCL low (during blue bar time.)
  3. The data is sampled (received) when SCL rises (green) for the first bit (B1).
  4. This process repeats, SDA transitioning while SCL is low, and the data being read while SCL is high (B2, Bn).
  5. A STOP bit (P) is signaled when SDA is pulled high while SCL is high.

In order to avoid false marker detection, SDA is changed on the SCL falling edge and is sampled and captured on the rising edge of SCL.

At the physical layer, both SCL and SDA lines are of open-drain design, thus, pull-up resistors are needed. Pulling the line to ground is considered a logical zero while letting the line float is a logical one. This is used as a channel access method. High speed systems (and some others) also add a current source pull up, at least on SCL; this accommodates higher bus capacitance and enables faster rise times. An important consequence of this is that multiple nodes may be driving the lines simultaneously. If any node is driving the line low, it will be low. Nodes that are trying to transmit a logical one (i.e. letting the line float high) can see this, and thereby know that another node is active at the same time.

When used on SCL, this is called clock stretching and gives slaves a flow control mechanism. When used on SDA, this is called arbitration and ensures there is only one transmitter at a time.

When idle, both lines are high. To start a transaction, SDA is pulled low while SCL remains high. Releasing SDA to float high again would be a stop marker, signaling the end of a bus transaction. Although legal, this is typically pointless immediately after a start, so the next step is to pull SCL low.

Except for the start and stop signals, the SDA line only changes while the clock is low; transmitting a data bit consists of pulsing the clock line high while holding the data line steady at the desired level.

While SCL is low, the transmitter (initially the master) sets SDA to the desired value and (after a small delay to let the value propagate) lets SCL float high. The master then waits for SCL to actually go high; this will be delayed by the finite rise-time of the SCL signal (the RC time constant of the pull-up resistor and the parasitic capacitance of the bus), and may be additionally delayed by a slave’s clock stretching.

Once SCL is high, the master waits a minimum time (4 μs for standard speed I²C) to ensure the receiver has seen the bit, then pulls it low again. This completes transmission of one bit.

After every 8 data bits in one direction, an “acknowledge” bit is transmitted in the other direction. The transmitter and receiver switch roles for one bit and the erstwhile receiver transmits a single 0 bit (ACK) back. If the transmitter sees a 1 bit (NACK) instead, it learns that:

  • (If master transmitting to slave) The slave is unable to accept the data. No such slave, command not understood, or unable to accept any more data.
  • (If slave transmitting to master) The master wishes the transfer to stop after this data byte.

During the acknowledgment, SCL is always controlled by the master.

After the acknowledge bit, the master may do one of three things:

  • Prepare to transfer another byte of data: the transmitter set SDA, and the master pulses SCL high.
  • Send a “Stop”: Set SDA low, let SCL go high, then let SDA go high. This releases the I²C bus.
  • Send a “Repeated start”: Set SDA high, let SCL go high, and pull SDA low again. This starts a new I²C bus transaction without releasing the bus.

One of the more significant features of the I²C protocol is clock stretching. An addressed slave device may hold the clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The master that is communicating with the slave may not finish the transmission of the current bit, but must wait until the clock line actually goes high. If the slave is clock stretching, the clock line will still be low (because the connections are open-drain). The same is true if a second, slower, master tries to drive the clock at the same time. (If there is more than one master, all but one of them will normally lose arbitration.)

The master must wait until it observes the clock line going high, and an additional minimum time (4 μs for standard 100 kbit/s I²C) before pulling the clock low again.
Although the master may also hold the SCL line low for as long as it desires, the term “clock stretching” is normally used only when slaves do it. Although in theory any clock pulse may be stretched, generally it is the intervals before or after the acknowledgment bit which are used. For example, if the slave is a microcontroller, its I²C interface could stretch the clock after each byte, until the software decides whether to send a positive acknowledgment or a NACK.

Clock stretching is the only time in I²C where the slave drives SCL. Many slaves do not need to clock stretch and thus treat SCL as strictly an input with no circuitry to drive it.
I²C is appropriate for peripherals where simplicity and low manufacturing cost are more important than speed. Common applications of the I²C bus are:

  • Reading configuration data from EEPROMs on SDRAM, DDR SDRAM, DDR2 SDRAM memory sticks (DIMM) and other stacked PC boards
  • Accessing low speed DACs and ADCs.
  • Changing contrast, hue, and color balance settings in monitors (Display Data Channel).
  • Changing sound volume in intelligent speakers.
  • Controlling OLED/LCD displays, like in a cellphone.
  • Reading real-time clocks.
  • Turning on and turning off the power supply of system components.
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