SPI Protocol

SPI_single_slaveThe Serial Peripheral Interface or SPI Bus is a four wire master/slave full duplex synchronous bus named by Motorola. Multiple slave devices can be hooked by utilizing chip select lines. It is used for short distance, single master communication, for example in embedded systems, sensors, and SD cards.

The bus is composed of two data pins, one clock pin, and one chip select pin:

  • SCLK – Serial Peripheral Interface Clock Signal (generated by the master) (also referred to as SCK)
  • MOSI – Master Out Slave In data (output from the master)
  • MISO – Master In Slave Out (output from the slave)
  • CS – Chip Select (also referred to as Slave Select (SS))

The SPI bus can operate with a single master device and with one or more slave devices. If a single slave device is used, the SS pin may be fixed to logic low if the slave permits it. Some slaves require a falling edge of the chip select signal to initiate an action, an example is the Maxim MAX1242 ADC, which starts conversion on a high→low transition.

SPI_three_slavesWith multiple slave devices, an independent SS signal is required from the master for each slave device. Most slave devices have tri-state outputs so their MISO signal becomes high impedance (logically disconnected) when the device is not selected. Devices without tri-state outputs cannot share SPI bus segments with other devices; only one such slave could talk to the master, and only its chip select could be activated.

Each slave may operate at different clock frequencies as well as different clock polarities and clock phases with respect to the data. The permutations of polarities and phases are referred to as SPI modes. Before beginning the communication, the bus master first configures the clock and the modes. The master then transmits the logic 0 for the desired chip over the chip select line. If a waiting period is required (such as for analog-to-digital conversion), then the master must wait for at least that period of time before starting to issue clock cycles.

During each SPI clock cycle, a full duplex data transmission occurs:

  • the master sends a bit on the MOSI line;the slave reads it from that same line
  • the slave sends a bit on the MISO line; the master reads it from that same line

SPI_8-bit_circular_transferTransmissions normally involve two shift registers of some given word size, such as eight bits, one in the master and one in the slave; they are connected in a ring. Data is usually shifted out with the most significant bit first, while shifting a new least significant bit into the same register. After that register has been shifted out, the master and slave have exchanged register values. Then each device takes that value and does something with it, such as writing it to memory. If there is more data to exchange, the shift registers are loaded with new data and the process repeats.

Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops toggling its clock. Normally, it then deselects the slave. Transmissions often consist of 8-bit words. A master can initiate multiple such transmissions if it wishes/needs. However, other word sizes are also common, such as 16-bit words for touchscreen controllers or audio codecs or 12-bit words for many digital-to-analog or analog-to-digital converters. Every slave on the bus that has not been activated using its chip select line must disregard the input clock and MOSI signals, and must not drive MISO. The master must select only one slave at a time.

The timing diagram is shown below. The timing is further described below and applies to both the master and the slave device.
At CPOL=0 the base value of the clock is zero

  • For CPHA=0, data are captured on clock’s rising edge and data is propagated on a falling edge.
  • For CPHA=1, data are captured on clock’s falling edge and data is propagated on a rising edge.

At CPOL=1 the base value of the clock is one (inversion of CPOL=0)

  • For CPHA=0, data are captured on clock’s falling edge and data is propagated on a rising edge.
  • For CPHA=1, data are captured on clock’s rising edge and data is propagated on a falling edge.

SPI_timing_diagramThe data must be stable for a half cycle before the first clock cycle. The MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next clock transition. SPI master and slave devices may well sample data at different points in that half cycle.

The full-duplex capability makes SPI very simple and efficient for single master/single slave applications. Some devices use the full-duplex mode to implement an efficient, swift data stream for applications such as digital audio, digital signal processing, or telecommunications channels, but most off-the-shelf chips stick to half-duplex request/response protocols.

SPI is used to talk to a variety of peripherals, such as

  • Sensors: temperature, pressure, ADC, touchscreens, video game controllers
  • Control devices: audio codecs, digital potentiometers, DAC
  • Camera lenses: Canon EF lens mount
  • Communications: Ethernet, USB, USART, CAN, IEEE 802.15.4, IEEE 802.11, handheld video games
  • Memory: flash and EEPROM
  • Real-time clocks
  • LCD, sometimes even for managing image data
  • Any MMC or SD card (including SDIO variant)
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